Communication device with configurable sigma-delta modulator

ABSTRACT

In up-to date communication devices an intermediate frequency signal is generated at first in a digital way and than is converted to an analogue signal by a digital-to-analogue converter ( 10 ). In order to offer a greater flexibility in choosing a particular digital-to-analogue converter ( 10 ) the invention proposes to use sigma-delta modulators ( 8 ), the output bit width (n) of which is arranged to be configurable. The advantage of providing sigma-delta modulators with a configurable output bit width is that by this the output bit width of the interpolation filters can be easily adapted to the input bit width of a choosen digital-to-analogue converter without the need to change the internal design of a baseband processing circuit.

FIELD OF THE INVENTION

[0001] The present invention relates to a method for digital generationof an analogue quadrature modulated radio signal as disclosed in thepreamble of claim 1, and to a communication devices or a circuit for acommunication device making use of this method.

DESCRIPTION OF THE PRIOR ART

[0002] A method for quadrature modulation and digital-to-analogueconversion of a sampled and digitally represented input signal in formof a complex baseband signal, represented by an in-phase and aquadrature-phase component is known for instance from WO 98/20657. Inthe prior art each component signal is separately sampled at a samplingrate sufficiently high to achieve a desired quantization noise shaping.By means of sigma delta modulation the noise signal is shaped spectrallyto have its energy essentially outside the frequency band of the inputsignal. The signal components I and Q are quadrature modulated to acarrier frequency equal to exactly one quarter of the sampling rate forthe quadrature modulated signal, so that repeated spectra of themodulated signal can thereby be found around all odd multipliers of thecarrier frequency. Usually digital quadrature modulation of I and Q iscarried out at a quarter of the sampling rate, as at this sampling ratethe multiplication of I and Q with a sine and a cosine signal can beeasily achieved with multiplying with a repeated sequence of [0, 1, 0,−1 and [1, 0, −1, 0] respectively. In practice this is carried out byinverting every second sample of each signal and instead of adding thetwo signals a multiplexer switches alternatively to that signalcomponent, that is not subject to a multiplication with the factor zero.The digital samples at the output of the multiplexer are converted bymeans of a digital-to-analogue converter to a corresponding analogueintermediate frequency (IF) signal. This IF signal is then up-convertedin a conventional way to a desired transmitter frequency.

[0003] In the cited prior art a sigma-delta modulation in connectionwith oversampling is used so that the quantization noise of thedigital-to-analogue conversion is shaped spectrally so that most of thisnoise ends up outside the frequency band of interest. As for reasons ofsimplicity the output signal of the sigma-delta modulators is only onebit a very high oversampling factor (a fact an oversampling factor F=20has been mentioned) has to be chosen. Also a repetition of sample valuesis foreseen so that the sample rate of the in-phase and quadraturesignal each separately are represented by only half of the sampling rateof the quadrature modulation.

[0004] Among other reasons like power consumption and dimensions of acommunication device a lot of the aforementioned functions are carriedout by a software controlled digital signal processor or in a morehardware orientated solution are integrated in an integrated circuit.Also hardware programmable logic circuits like Application SpecificIntegrated Circuits (ASICs) are common. If a one bit digital-to-analogueconverter is used this digital-to-analogue converter could be integratedwith all the other functions like filters, sigma-delta modulators in asingle circuit. As in practise design restrictions, e.g. clock rates,have to be observed over-sampling could not be increased without anylimits. By using a digital-to-analogue converter with a higher bit widthat the input the over-sampling rate could be reduced. For performanceand economic reasons this will often mean that a separatedigital-to-analogue converter from a third party supplier has to be usedinstead of an integrated one.

[0005] The electrical properties of available third party supplier aresubjected to changes. From time to time it may even happen that acertain circuit is discontinued. As a result of this the basebandprocessing device will have to be partly redesigned.

SUMMARY OF THE INVENTION

[0006] It is an object of the invention to introduce a concept thatoffers a greater flexibility in adapting baseband processing to specificneeds and to save investments in circuit design and development costs.

[0007] This object is achieved by using a sigma-delta modulator, theoutput bit width of which is arranged to be configurable.

[0008] The advantage of providing sigma-delta modulators with aconfigurable output bit width is that by this the output bit width ofthe interpolation filters can be easily adapted to the input bit widthof a chosen digital-to-analogue converter without the need to change theinternal design of a baseband processing circuit. By this the samebaseband processing circuit can be used without modifications withdifferent digital-to-analogue converters. Thus the most appropriatedigital-to-analogue converter can be chosen from an up-to-date supply.For instance if a certain analogue-to-digital converter with certainproperties like signal-to-noise ratio is at the moment available only asa 14-bit-DAC it is possible to switch later on e.g. to a 12-bit DACwhich provides the same properties but at a lower price.

[0009] Preferably the output bit width is made adjustable by means ofcontrol information like a control data word or input terminals whichhave to be set to a certain voltage level, e.g. by jumpers or solderstraps so that the sigma-delta modulators are (re-)configurable atminimum efforts and costs.

[0010] The usage of digital-to-analogue converters with a higher numberof input bits also makes it possible to use a lower over-samplingfactor. Among others this has a positive effect on power consumption. Onthe other hand one might have to face a drawback in accuracy by anincrease phase error between the samples of the in-phase and quadraturesamples. Corresponding on the individual application this phase errormight not be longer tolerable.

[0011] Appropriate phase correction methods according to claims 2, 3 or4, especially that of claim 2 or circuit designs according to claims 7,8, 9 provide the advantage that they can be easily integrated in theinterpolation filter arrangement by just changing the filtercharacteristics. As the interpolation filters have to be present anywayno additional hardware circuits have to be spent for the purpose of amutual phase shift between the in-phase and the quadrature signal.

[0012] A preferred embodiment to make the output signal of a sigma-deltamodulator configurable is achieved by a circuit arrangement according toclaim 6. This arrangement has the advantage that only simple logic gateshave to be provided as switches in some of the output lines of thesigma-delta modulators. Thus this is a very simple solution with verylow circuital erogation.

BRIEF DESCRIPTION OF THE INVENTION

[0013] In the following the invention will be further describedaccording to the figures and by means of examples

[0014]FIG. 1: Block diagram of a Wideband CDMA radio transmitter

[0015]FIG. 2 First embodiment of a filter arrangement, sigma-deltamodulator, IQ-modulator and digital-to analogue converter

[0016]FIG. 3 Second embodiment of a filter arrangement, sigma-deltamodulator, IQ-modulator and digital-to analogue converter

[0017]FIG. 4 Circuit arrangement of an configurable sigma-deltamodulator

[0018]FIG. 5 Spectra of a digital IF signal and quantization noisewithout sigma-delta modulation

[0019]FIG. 6 Spectra of a digital IF signal and quantization noise withsigma-delta modulation

[0020] As an embodiment of the invention a transmitter for wideband codedivision multiplex access (W-CDMA) communication systems has beenchosen. W-CDMA, as it is designed and standardised at the moment by 3GPP(third generation partnership project), provides direct sequencespreading to allow different users to share a common carrier frequencyband by applying uniquely assigned code sequences, so-called spreadingcodes to their data. It is a general property of direct sequencespreading that the data rate of the spreading codes is always higherthan the data rate of the user data. To distinguish the bits of the userdata from the bits of the spreading code a bit of the spreading code iscalled chip and the data rate of the spreading code therefore chip rate.The sum of all signals in a CDMA frequency band appears statistically asa random signal, comparable to a noise signal. As the spreading codesare usually chosen in a way that they are orthogonal a receiver with theknowledge of a particular used spreading code is capable to extract asignal transmitted by a specific user from that “noise signal”.

[0021] To improve the performance of 3GPP W-CDMA systems the spreadingcodes are composed of two separate codes in a way that preserves theorthogonal properties of these codes. A first code is used todistinguish different users in a cell from each other. As by this firstcode a separate physical channel can be assigned to each user (in thesame frequency band) this first code is called channel code c_(ch). Asthe codes are constituted in an appropriate way it is very easy to adaptthe data rate of each channel by assigning a channel code with anappropriate length. A second code, the scrambling code c_(scramb) isused to distinguish neighboured or overlaid cells.

[0022]FIG. 1 shows a block diagram of a radio transmitter according tothe invention designed for a base station of a W-CDMA system in which upto the generation of a first intermediate frequency (IF) signal allsignals are processed exclusively as digital signals. The digitallygenerated intermediate frequency signal is then converted to an analoguesignal and up-converted to a desired transmitter radio frequency signal.Although there are some design differences in the W-DCMA system betweenup-link and down-link in order to be concise in the following only thetransmitter for a base station will described as the design differencesdo not affect the subject of the invention.

[0023] Binary user data b, which is a multiplexed binary data stream ofuseful bits (e.g. digital encoded speech signals) and controlinformation is encoded and interleaved in an encoder and interleaver 1.As in down-link the W-CDMA systems applies a QPSK-modulation scheme,every two succeeding bits of the binary data stream at the output of theinterleaver 1 are mapped by a base band modulator 2 to a complex baseband format, consisting of an in-phase component i and a quadraturecomponent q. Each component is still a binary signal. To distinguish thedata of different users a channel spreader 3 multiplies each base bandsignal component i, q with a binary channel code sequence c_(ch) thathas been assigned individually to each user. Thus the output signal ofthe channel spreader 3 is still a binary signal. To adjust the outputpower of each channel the channel coded in-phase and quadrature binarysignals are multiplied by gain control means 4 with a gain factor GAINgiving samples with a bit width greater than one. In this embodiment thebit width of those samples has been chosen to fourteen bits.

[0024] For reasons of clarity up to here only the processing of a singlechannel has been described. In a base station of course a multitude N ofchannels is processed in parallel. To form a single wideband outputsignal the in-phase and the quadrature components i,q of all thesechannels I . . . N are summed up separately by two adders 5 giving sumsignals I and Q. By means of a complex multiplier 6 these signals aremultiplied with the complex scramble code c_(scramb). Each scrambledcomponent signal I′, Q′ is then processed separately again. As in 3GPPthe chip rate of the scrambling code sequence c_(scramb) has been fixedto 3,84 mega chips per second (Mcps) the sample rate of the twoscrambled component signals I′, Q′ is increased by scrambling to thisvalue.

[0025] By means of a digital filter arrangement 7 the component signalsI′, Q′ are shaped and up-sampled to 30,72 Msps. Then the up-sampledcomponent signals are fed each via sigma-delta modulators 8 to anIQ-modulator 9, which generates an output signal of 61,74 Msps. Adigital-to-analogue analogue converter (DAC) 10 converts the outputsignal of the IQ-modulator 9 to an analogue signal.

[0026] By means of the interpolation filter arrangement 7 the bit widthof the samples is increased in this embodiment of the invention fromfourteen bits to sixteen bits. According to the invention thesigma-delta modulators 8 have been provided each with a preset input 80where a preset value S can be set in order to determine the bit width nof the samples at the sigma-delta modulators 8 outputs. Thus the bitwidth n of the samples at the output of the sigma-delta modulators 8 canbe adjusted that it corresponds to the resolution (=bit width of inputsamples) of the digital-to-analogue converter 10. As the IQ-modulator 9only multiplexes the in-phase and quadrature samples or the invertedsamples respectively it does not change the bit width of the samples.

[0027] Due to the over-sampling of the filter arrangement 7 there wouldbe two analogue signals, one at 15,36 MHz and one at 46,08 MHz. As at ahigher frequency a DAC has a lower performance, e.g. resulting in alower signal to noise ratio, the 46,08 MHz signal is suppressed by thefilter arrangement 7 as well as by a conventional band pass filter 11 atthe output of the DAC 10. Thus only the 15,36 MHz signal is used forup-converting this analogue signal in an up-converter arrangement 12.The up-converted RF signal is then amplified by a power amplifier 13 andfed to an antenna 14.

[0028] By reference to FIG. 2 the interaction of the filter arrangement7, the sigma-delta modulators 8 and the IQ-modulator 9 is elucidated inmore detail. The filter arrangement 7 is composed of two parallel filterbranches. One branch for the in-phase samples I′ and one branch for thequadrature samples Q′ . The primary purpose of the filter arrangement 7is to prevent out-of-band emissions by means of pulse shaping. In orderto reduce the total number of filter taps an arrangement of up-samplingstages and pulse shaping filter has been chosen where identical pulseshaping filters 15 are placed at the input of each filter arrangement 7.Interpolation filters 16, 17 are connected to the output of the pulseshaping filters 15 for up-sampling and interpolating the values of thehereby inserted samples. As the best way of interpolating it has beenfound to use a cascade of filter stages 161, 162, 171, 172, each filterstage 161, 162, 171, 172, inserting and interpolating only one newsample between two existing samples.

[0029] At first by means of the pulse-shaping filters 15 the componentsignals I′, Q′ are up-sampled for a first time. The pulse-shapingfilters 15 are implemented as finite impulse response filters with rootraised cosine (RRC) characteristic with a data word width of sixteenbits at their outputs. Due to up-sampling the sample rate of each of thetwo component signals I′, Q′ at the output of the pulse-shaping filter15 is doubled to 7,68 Msps.

[0030] The spectrally shaped signals are then up-sampled by the cascadeof two digital interpolation filter stages 161, 162 for the in-bandsignal component I′ and by the cascade of filter stages 171, 172 for thequadrature component Q′ of the complex base band signal. In each filterstage 161, 162, 171, 172 one interpolated sample is inserted betweeneach two samples of the input signal thus doubling the output data rateat the output of an interpolating filter in respect to the data rate atthe input of each filter stage. The interpolation filter stages 161,162, 171, 172 are implemented as half band filters and are also used tosuppress the image of the RRC filter which appears when increasing thesampling rate of a factor by two. After having been up-sampled twotimes, each time by a factor of two, the sample rate of the outputsignal of the last filter stages 162, 172 is 30,72 Msps. In thisembodiment the interpolation filter stages do not change the bit widthof their samples so that at the output of the filter stages 161, 162,171, 172 the bit width is still sixteen bits.

[0031] The output data of each last filter stage 162, 172 is fed to twoidentical sigma-delta modulators 8 in order to adapt the bit width m ofthe filtered samples of sixteen bits to the bit width n of the digitalto analogue converter (DAC) 10. In the embodiment of the inventionswitches 80 are used to set the bit width n of the sigma-deltamodulators 8 output samples thus that it corresponds to the inputresolution of a particular used DAC 10.

[0032]FIG. 4 shows a preferred embodiment of a configurable sigma-deltamodulator 8 consisting of a 16-bit adder 81, a feedback switch 82, aquantization error filter 83, and a control decoder 84 for controllingthe feedback switch 82. The 16-bit adder 81 provides two 16-bit inputports. One input port 811 represents the input of the sigma-deltamodulator 8 the other input port 812 is used as feedback input for thequantization error. The feedback switch 82 is inserted between the eightleast significant bits of the adder's 81 output port and the outputlines of the sigma-delta modulator 8. It is used to switch a variablenumber of least significant bit carrying output lines of the output portof the adder 81 through to the output of the sigma-delta modulator or tothe input lines of the quantization error filter 83.

[0033] In the preferred embodiment a eigth-bit latch is used asquantization error filter 83. The latch 83 is clocked with the sampleclock of the input samples and therefore delays its input samples forexact one sample period. The delayed samples are fed to the second inputport of the adder 81. As only a maximum number of eight bits is fed backto the least significant bit carrying input lines of the feed back inputport 812 of the adder 81, the eight most significant bit carrying inputlines are set permanently to the binary value zero.

[0034] The number of lines fed back via the latch 83 could be variedbetween one and eight, thus setting the output resolution of thesigma-delta-modulators 8 to a value between fifteen and eight bit. Inorder to control the eight according switching states of the feedbackswitch 82 with a minimum of control terminals the control decoder 84 isused to convert a three-bit binary value to corresponding switchingstates. For instance if all input control terminals of the controldecoder 84 are set to a value of zero the feedback switch 82 iscontrolled thus that only the least significant output line of the adder81 is fed to the latch 83, if the input control terminals are set to avalue of one the least two significant output lines are fed back and soon.

[0035] If a configuration is expected to be changed seldom solder strapscan be used to set the input control terminals 80 of the control decoder84 to appropriate voltage levels. If a configuration is subjected toperpetual changes so-called jumpers or micro switches would beappropriate for more convenience. Another possibility is to realize thedecoder as a software controlled device where the configurationinformation is transmitted to that control decoder from e.g. aconfiguration memory via an internal control bus.

[0036] The feedback switch 82 may be build by an array of change-overswitches. A very simple embodiment of the feedback switch 82 can beachieved by using two AND gates 821, 822 for each line to be switched.The respective output line of the adder 81 to be switched is connectedto each first inputs of the both AND gates 821, 822. The output of oneAND gate 821 represents the respective output of the sigma-deltamodulator 8, the output of the other AND-gate 822 is connected to anrespective input of the latch 83. An respective output of the controldecoder 84 is fed to the other input of the one AND gate 821 with itsnon-inverted value and to the other AND gate 822 with its invertedvalue. Thus, depending of the value of the control decoder's output ifthe respective output of the adder 81 shows a logical “1” this value ispassed to the output of the sigma-delta-modulator or to the latch 83respectively. In all other cases the outputs of the AND gates 821, 822show a logical “0”.

[0037] By adding the quantization error to the input signal of thesigma-delta modulator 8 the quantization error is averaged. Thus bymeans of the sigma delta modulators 8 the resolution loss at thetransition from high-resolution digital samples to digital samples withreduced resolution is compensated to a great amount or even improved.This means that for a relatively high sample rate a less expensive DACcan be chosen and despite the resolution loss the whole arrangementstill benefits from the higher resolution used in the filter stages 161,162, 171, 172.

[0038] The output signal of each sigma-delta modulator 8 is input to theIQ-modulator 9. For the following explanation let us assume the samplesI0, I1, I2, I3, I4, I5, I6, . . . and Q0, Q1, Q2, Q3, Q4, Q5, Q6, . . .represent a stream of in-phase and quadrature samples. A perfectIQ-modulator would assemble a data stream like I0, Q1, −I2, −Q3, I4, Q5,−I6, . . . This yields a correct output sequence, the even indexedI-samples are interleaved with the odd indexed Q-samples (or vice versa,depending on the sample the data stream is starting with). Thus thesample rate of the in-phase and quadrature signal corresponds exactly tothe sample rate of the output signal of the IQ-modulator. In the presentembodiment for the output data stream of the IQ-modulator 9 only odd oronly even samples of the ideal data streams are used giving a datastream like I0, Q0, −I2, −Q2, I4, Q4, I6, . . . But by this a phaseshift error between the in-phase and quadrature component is introduced.This phase shift error can be neglected if the sample rate respectivethe interpolation factor is very high.

[0039] In the case of the described embodiment the over-sampling factoris moderate (about six) so that the phase error is in the range of 3%.In 3GPP W-CDMA this phase error will violate the system specifications.To compensate this phase shift error in the preferred embodiment of theinvention it has been considered to be the most efficient implementationto apply a mutual time shift between the in-phase and quadraturecomponent at the last filter stages 162, 172. In principal a mutual timeshift can be achieved by interpolating only one of the component signalsI′ or Q′ with a factor of two. The resulting interpolated values willcorrespond to the required time shifted values. But this requires atsupplementary interpolation filter that runs at a doubled clock rate.The preferred embodiment gets along without a rise in the clockfrequency. For this purpose one of the two last filter stages 152, 162is designed as a filter with even order (=even indexed coefficients) andthe other last filter stage is designed as a filter with odd order (=oddindexed coefficients). Such filters can be designed and optimizedindependent from each other. Especially, if like in this embodiment, thelast interpolation is by a factor of two, half-band filters are mostefficient and perform best. Due to the high sampling rate filters withlow orders are sufficient, e.g. a six-order-filter for the in-phasesamples and a seven-order-filter for the quadrature samples.

[0040]FIG. 5 shows the spectra of the digital IF signal and quantizationnoise without sigma delta modulation and FIG. 6 shows the same spectraif the described sigma delta modulation is applied to a W-CDMA signal.The bandwidth of the signal is 5 MHz with root raised cosine shape. Thesample rate is 65.536 Msps yielding a digital IF of 16.384 MHz. Thesignal is quantized to twelve effective bits meaning that four bits ofthe sixteen bit output of the sigma-delta modulator is fed back. Thesigma delta modulators in the in-phase and quadrature signal lines areof first order. Calculating the signal to noise ratio in the signal bandshows an improvement of the dynamic range of 13 dB. In contrast heretothe theoretical increase of the signal-to noise ratio while using a16-bit DAC is only 12 dB. That means that by means of the sigma-deltamodulation the signal-to-noise ratio is even better. This effect can befurther enhanced with a higher order sigma delta modulator.

[0041] The signal to noise ratio in the adjacent channel, 5 MHz of thesignal's centre frequency and in the next adjacent channel 10 MHz of thesignals centre frequency is 4 dB, about the same in both cases. However,if a higher interpolation in connection with a DAC with a highersampling rate will be used, the dynamic range could be improved further.That gives the opportunity to gain a higher intermediate frequency byusing faster DAC with lower bit resolution.

[0042] Preferably first order sigma-delta modulator are used as thosesigma-delta modulators can be implemented without a multiplier. Thusthey can be easily operated at a high clock rate and are not a speedlimiting element. Of course also sigma delta modulators of higher ordercan be designed with a configurable number of output lines.

[0043] Another embodiment of the interpolation filter is shown in FIG.3. The last interpolation filter stages 152, 153 in the in-phase andquadrature signal paths are chosen identical. The missing samplesbetween the output samples of the last interpolation filters have to beinterpolated in one of the two signal branches. For that purpose aninterpolation filter with factor two can be used where all arithmeticfunctions are removed which compute those samples that are not used bythe IQ-modulator 9. For example in a typical half-band filter, with theexception of the centre coefficient every second coefficient is zero. Asa consequence these filters can be divided into two parts running athalf of the output sample rate. The first part just multiplies the inputsamples with the centre coefficient and thus leaves the input sequenceunaffected apart from another amplitude scaling. The second partcomputes the intermediate, i.e. interpolated samples, by a weighted sumof all other nonzero coefficients. Consequently, the first part can beremoved. The remaining interpolator 18 operates at the same clock rateas the preceding interpolation filter stage 162. The latency of theremaining interpolator 18 has to be compensated by a simple delaycircuit 19 in the other signal branch. This delay circuit 19 could beeasily realised by an adequate number of shift registers.

[0044] The previously described embodiments apply the time shift in amost efficient way. Of course there are also other possibilities tointroduce a time shift. In case of spectral shaping based on fastFourier transform a phase shift can be achieved by multiplying thefrequency domain function with exp(jφ), where φ corresponds to a timeshift 1/f_(s) and f_(s) is the sampling rate. In case of the presentW-CDMA system spectral shaping is done with an interpolationroot-raised-cosine (RRC) filter realised by a high order finite impulseresponse (FIR) filter. A phase respective a time shift can easiest beintroduced if the filter is designed from the analytical description ofits impulse response h. In practise the time length is truncated. Bestcharacteristics with time limited impulse response h are obtained bywindowing with a Kaiser-Bessel window in the time domain. The filtercoefficients of an interpolating RRC filter of order N with roll-offfactor η and interpolation factor r thus can be calculated by$\begin{matrix}{h_{n,\tau} = {\frac{4\eta}{{4\eta} + {\pi \left( {1 - \eta} \right)}} \cdot \frac{{n^{\prime} \cdot {\cos \left\lbrack {{\pi \left( {1 + \eta} \right)} \cdot n^{\prime}} \right\rbrack}} + {\sin \left\lbrack {{\pi \left( {1 - \eta} \right)} \cdot n^{\prime}} \right\rbrack}}{n^{\prime}\left\lbrack {1 - \left( {4{\eta \cdot n^{\prime}}} \right)^{2}} \right\rbrack} \cdot w_{n}}} \\{{{with}\quad n^{\prime}} = \frac{n - \tau - \frac{N}{2}}{r}}\end{matrix}$

[0045] where τ is the time shift, w_(n) is the window function and h_(n)is normalized such that h(0)=1. If the sample rate after the RRC filteris f_(s)/m, τ has to be 1/m in one of the in-band or quadrature branchesand zero in the other to compensate the time shift in the base bandmodulator. τ can be chosen positive or negative depending on the mutualphases of the modulation sequences.

[0046] Another option is to have different τ for the in-phase andquadrature signal path, e.g. τ(I)=½ m and τ(Q)=−½ m or vice versa or anyother values yielding an appropriate delay difference between thein-phase and quadrature signal path. The drawback of a nonzero timeshiftfilter is that the filter coefficients become unsymetrical around t=0what means a higher resources than an implementation as a symetricalfilter.

[0047] Usually the interpolation filtering with factor m after thespectral shaping is not done in one single step but distributed over acascade of interpolation filters with as low as possible interpolationfactors, i.e. in steps of the prime factors of m where the lower factorsare at the beginning and the higher factors at the end of the cascade.This is considered to be the most efficient way of implementation sinceit yields the lowest numbers of filter taps and thus arithmeticoperations.

[0048] Another possibility is to introduce the time shift within theinterpolation filter stages. The time shift can be introduced anywherein the filter cascade, however, the design of the concerning filter mustbe based on an analytical description of the impulse response as in thecase of the RRC filter. A good solution seems to be a raised-cosinecharacteristic for which the filter coefficients may be calculated by$h_{n,\tau} = {\frac{{\sin \left( {\pi \cdot n^{\prime}} \right)} \cdot {\cos \left( {\pi \quad {\eta \cdot n^{\prime}}} \right)}}{\pi \cdot n^{\prime} \cdot \left\lbrack {1 - \left( {2{\eta \cdot n^{\prime}}} \right)^{2}} \right\rbrack} \cdot w_{n}}$

[0049] The difference of τ between the corresponding filters in thein-phase and quadrature branch is 1/m′, where m′ is the remaininginterpolation factor after this filter stage.

[0050] Furthermore it has be mentioned again that the invention is notrestricted to the specific embodiments and examples described in thepresent invention. That is, on the basis of the teaching contained inthe description, various modifications and variations of the inventionmay be carried out. For example the usage of an intermediate frequencysignal should not be taken as a restriction of the invention toup-conversion transmitters. Provided digital components with aprocessing speed that matches to the desired radio frequency are appliedalso a direct generation of the radio frequency, without the need ofgenerating an intermediate frequency signal is feasible and laystherefore within the scope of the invention. Also the invention is notrestricted to devices for cellular phones, also communication systemswithout central stations like point-to-point radio link systems orpush-to-talk phones, like CB radio may take advantage of the claimedmodulation method.

1. Method for generating an analogue quadrature modulated radio signalfrom a digital input signal in form of a complex baseband signal,represented by samples of an in-phase (I) and a quadrature (Q) componentcomprising the steps of applying the samples of the in-phase signal (I)to a first interpolation filter (16) and the samples of the quadraturesignal (Q) to a second interpolation filter (17) for generatingup-sampled interpolated in-phase and quadrature-phase samples, eachsample having a certain bit width (m) applying the up-sampledinterpolated in-phase and quadrature-phase samples to sigma-deltamodulators (8) to form sigma-delta modulated in-phase andquadrature-phase samples whereby the bit width (n) of the sigma-deltamodulated samples is lower than the bit width (m) of the interpolatedsamples applying the in-phase and quadrature samples to a IQ-modulator(9) to form samples of an IQ-modulated signal applying the IQ-modulatedsamples to a digital-to-analogue converter (10) characterised in thatthe bit width (n) of the sigma-delta modulators is made configurable andthat the bit width (n) is set thus it matches the input bit width of thedigital-to-analogue converter (10).
 2. Method according to claim 1wherein a mutual time shift between the in-phase and quadrature samples(I′, Q′) is achieved by using for one of the component signals (I′) aninterpolation filter with even order and for the other component signal(Q′) an interpolation filter with odd order.
 3. Method according toclaim 1 wherein a mutual time shift between-the in-phase samples (I′)and the quadrature samples (Q′) is achieved by applying an interpolationto either the in-phase samples (I′) or to the quadrature samples (Q′),whereby for that interpolation filter all arithmetic functions areremoved which compute samples that are not used by the IQ-modulation. 4.Method according to claim 1 wherein a mutual time shift between thein-phase samples (I′) and the quadrature samples (Q′) is achieved byimplementing a spectral shaping filter on base of a fast Fouriertransform and multiplying the frequency domain function with exp(jφ),where φ corresponds to a time shift 1/f_(s) and f_(s) is the samplingrate.
 5. Communication device with an circuit arrangement for generatingan analogue signal from a digital input signal in form of a complexbaseband signal, represented by samples of an in-phase and a quadraturecomponent (I′, Q′) comprising a first interpolation filter (16) forgenerating up-sampled in-phase samples from the said in-phase inputsamples, each sample having a first bit width (m) a first sigma-deltamodulator (8) to which the interpolated in-phase samples are input to,generating sigma-delta modulated in-phase output samples of a second bitwidth (n), whereby the bit width of the sigma-delta modulated samples islower than the bit width of the interpolated in-phase signal a secondinterpolation filter (17) for generating up-sampled quadrature samplesfrom the said in-phase input samples, each sample having the said firstbit width (m) a second sigma-delta modulator (8) to which theinterpolated quadrature samples are input to, generating sigma-deltamodulated quadrature output samples of a second bit width (n), wherebythe bit width of the sigma-delta modulated samples is lower than the bitwidth of the interpolated in-phase signal an IQ-modulator for generatingfrom said sigma-delta modulated in-phase and quadrature samples a streamof IQ-modulated samples and a digital-to-analogue converter (10) forgenerating from that stream of IQ-modulated samples said analogue signal(IF) characterized in that a control circuit arrangement (82, 84) isprovided for controlling the bit width (n) of the output samples of saidsigma-delta modulators
 8. 6. Communication device according to claim 5wherein the sigma-delta modulator (8) is comprising at least one adder(81) having a plurality of output lines and at least one quantizationerror filter (83) and wherein said control circuit arrangement (82, 84)comprises at least one switch (821, 822) which is inserted in at leastone of the output lines of said adder (81) for switching in a firststate said output line of the adder (81) to the output of thesigma-delta modulator or in a second state for switching said outputline to said quantization error filter (83).
 7. Communication deviceaccording to claim 5 or 6 wherein a mutual time shift between thein-phase samples and the quadrature samples is achieved by providing forone of the component signals an interpolation filter (162) with evenorder and for the other component signal an interpolation filter (172)with odd order.
 8. Communication device according to claim 5 or 6wherein a mutual time shift between the in-phase samples and thequadrature samples is achieved by applying an interpolation to eitherthe in-phase samples or to the quadrature samples, whereby in thatinterpolation filter all arithmetic functions are removed which computesamples that are not used by the IQ-modulator.
 9. Communication deviceaccording to claim 5 or 6 wherein a mutual time shift between thein-phase samples and the quadrature samples is achieved by implementinga spectral shaping filter on base of a fast Fourier transform andmultiplying the frequency domain function with exp(jφ), where φcorresponds to a time shift 1/f_(s) and f_(s) is the sampling rate. 10.Circuit for a communication device with input terminals for samples of acomplex baseband signal provided for samples of a first bit width andoutput terminals provided for output samples of a second bit widthcomprising interpolation filters (7), sigma-delta modulators (8) and anIQ-modulator (9) whereby control terminals (80) are provided to set thebit width (n) of the output signal thus that the bit width (n) of theoutput samples equals or is lower than the bit width of the inputsamples.